Numato Mimas V2 Tutorial

Just in time for Christmas I got a present from Numato Labs!  They have sent me a Mimas V2 FPGA development board!  *Really Huge Grin*

I thought the first thing I should do would be to write up a tutorial on how to get started using it. Here is a short video of me unboxing it!

For those who are not aware the Mimas V2 is an FPGA development board.  It’s basically a simple to use tool for people who would like to learn how to use an FPGA (Field Programmable Gate Array) device to complete complex engineering and programming tasks.  FPGA devices are quite complex and the learning curve can be quite steep.  A simple to use and program development board takes some of the load off.

Here are the specifications of the Mimas V2:

  • FPGA: Spartan XC6SLX9 in CSG324 package
  • DDR: 166MHz 512Mb LPDDR (MT46H32M16LF/W949D6CBHX6E)
  • Flash memory: 16 Mb SPI flash memory (M25P16)
  • USB 2.0 interface for On-board flash programming
  • FPGA configuration via JTAG and USB
  • 8 LEDs ,Six Push Buttons  and 8 way DIP switch for user defined purposes
  • VGA Connector
  • Stereo Jack
  • Micro SD Card Adapter
  • Three Digit Seven Segment Display.
  • 32 IOs for user defined purposes
  • Four 6×2 Expansion Connectors
  • On-board voltage regulators for single power rail operation

The key points to note from the above list is that we don’t need an expensive external programmer or complicated power supply, the board has lots of memory and plenty of ways to interface with the FPGA device!


In order to use the development board we will need to download a few bits and pieces from the Numato Website:
We will also need to download Xilinx Webpack ISE 14.7 and a licence file….and in order to that you will need to register with the Xilinx Website and then download the files as required.  It isn’t difficult but it might be confusing:

Once the software has downloaded you will need to install it.  Extract it to a suitable folder on your hard disk and then navigate to the install file xsetup.exe.  You will need to execute the setup and then let the software install.  The installation program will prompt you to respond to where you would like to install the software and which features you require.  Choose the default features (Webpack ISE) and continue.  At the end of the installation you will be prompted to obtain a licence file – make sure that you enter a suitable email address to receive the licence file.  You can’t program the Mimas V2 without it!
Once the software is installed run the Xilinx ISE 14.7 project Navigator (choose 32 bit or 64 bit as appropriate to your operating system)
Once the Xilinx project navigator software has loaded we need to start a new project – Exciting times! 
After that a new window will appear prompting you to select where on your hard disk you wish to store the project files and what you would like to name the project.  Choose somewhere suitable to store the files and call the project something appropriate.  Make sure you select HDL as the top level source – this means we will be typing in code to program the project, not drawing a schematic. Click ‘Next’ when ready:
The next screen prompts you to enter the specifications of the FPGA – Make sure your select the same settings as shown below, if you don’t your project may not compile and may not work!
Click ‘Next’ to continue onto the project summary screen.  Its a text file which confirms all of the information we just selected.  Click ‘Finish’ to close the window and return to the main Xilinx project screen:
Don’t be put off by all the menu items and toolbars. You will learn how to use them in time!  What we need to do now is create a new source file.  Right click on the box with the text ‘Empty view’ and add new source:
A new window will appear – select VHDL module and provide an appropriate file name:

Click ‘Next’ when you are ready to continue.  For this tutorial we are going to keep things simple!  Lets turn an LED on when we push an associated button.  I’ve chosen to have two inputs and two outputs and given them appropriate names:


Click ‘Next’ when you are ready to continue.  A summary screen giving the details we just selected will be provided.


Click ‘Finish’ and the source code template will be displayed in the main project window:


Any line which is in green and preceded by ‘–‘ is a comment.  Any word in dark blue is a ‘keyword’ and any text in purple relates to a library or method.  The Xilinx software has added a few comments relating to the source file.  I tend to delete them as they aren’t strictly necessary.  Cut out the comments (optional) and paste in the code below:

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-- Alex's Mimas V2 VHDL Tutorial
-- (c) 21-12-2014
-- A simple demonstration of a development board

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Mimas_V2_VHDL_Tutorial is
Port ( DIP1 : in STD_LOGIC;
DIP2 : in STD_LOGIC;
LED1 : out STD_LOGIC;
LED2 : out STD_LOGIC);
end Mimas_V2_VHDL_Tutorial;

architecture Behavioral of Mimas_V2_VHDL_Tutorial is

begin

LED1 <= DIP1;
LED2 <= DIP2;

end Behavioral;

The first three lines are comments about what the source code does.  Lines 5 and 6 tell the Xilinx compiler to use the standard library and notation.  Lines 8 to 13 tell the Xilinx compiler what inputs and outputs we want to use – two dip switches and two onboard LEDS.  The actual function (behaviour) the dip switches and LEDS perform is set by lines 19 and and 20.  LED1 is equal to the state that DIP switch 1 is at and the same for LED 2 and switch 2.

Now we need to tell the Xilinx compiler which pins are connected to what.  To do that we need to create an implementation constraints file.  Right click on the ‘Hierachy box’ and add a new source file.

Select ‘Implementation Constraints File’ and give it a suitable file name.

Click ‘Next’ when you are ready to continue and a summary window will be displayed:

Click ‘Finish’ to return to the main project window where the ICF file will be open and blank!  What we need to do is fill it.  To that we need to know how the Mimas V2 board is connected up – How are the DIP switches and LEDS and for that matter any peripheral devices connected to the FPGA?  The way to find out is to consult the manual and the schematic diagram.  The schematic diagram of interest is on page 29 of the manual.  The diagram is quite complex but if we look carefully we can see the bus connections of the DIP switches and LEDS:

We can choose to use any LED or any DIP switch we like.  I’m going to use LED1 and LED8 for the outputs and DIP switch 1 and DIP switch 2 for the inputs just to be different!  LED1 is connected to pin ‘P15′ and LED 8 is connected to pin ‘T17′.  The DIP switches are on pins ‘C17′ and ‘C18′.  From this information we can write the implementation constraints file.  Numato labs have helpfully provided a sample one.  All we need to do is modify it to suit our purposes.  Here is the sample file:

# This file is a .ucf for Mimas V2                                                                    #
# To use it in your project : #
# * Remove or comment the lines corresponding to unused pins in the project #
# * Rename the used signals according to the your project #
#+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++#

#********************************************************************************************************************#
# UCF for Waxwing Spartan 6 Development Board #
#********************************************************************************************************************#

CONFIG VCCAUX = "3.3" ;

NET "CLK" LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz;

NET "RST_n" IOSTANDARD = LVCMOS33 | PULLUP;


######################################################################################################################
# DIP Switches #
######################################################################################################################
NET "DPSwitch[0]" LOC = C17 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP;
NET "DPSwitch[1]" LOC = C18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP;
NET "DPSwitch[2]" LOC = D17 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP;
NET "DPSwitch[3]" LOC = D18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP;
NET "DPSwitch[4]" LOC = E18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP;
NET "DPSwitch[5]" LOC = E16 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP;
NET "DPSwitch[6]" LOC = F18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP;
NET "DPSwitch[7]" LOC = F17 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP;

######################################################################################################################
# Push Buttons Switches #
######################################################################################################################

NET "Switch[0]" LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP;
NET
"Switch[1]" LOC = L18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP;
NET
"Switch[2]" LOC = M16 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP;
NET
"Switch[3]" LOC = L17 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP;
NET
"Switch[4]" LOC = K17 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP;
NET
"Switch[5]" LOC = K18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP;

######################################################################################################################
# LEDs #
######################################################################################################################

NET "LED[0]" LOC = P15 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"LED[1]" LOC = P16 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"LED[2]" LOC = N15 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"LED[3]" LOC = N16 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"LED[4]" LOC = U17 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"LED[5]" LOC = U18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"LED[6]" LOC = T17 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"LED[7]" LOC = T18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;

######################################################################################################################
# Seven Segment Display #
######################################################################################################################

NET "SevenSegment[0]" LOC = A5 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"SevenSegment[1]" LOC = C6 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"SevenSegment[2]" LOC = D6 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"SevenSegment[3]" LOC = C5 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"SevenSegment[4]" LOC = C4 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"SevenSegment[5]" LOC = A4 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
    NET "SevenSegment[6]"     LOC = B4  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SevenSegment[7]" LOC = A3 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
# Enables for Seven Segment
  
NET "SevenSegmentEnable[2]" LOC = B3 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SevenSegmentEnable[1]" LOC = A2 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SevenSegmentEnable[0]" LOC = B2 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;

######################################################################################################################
# Audio #
######################################################################################################################
NET "Audio1" LOC = B16 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "Audio2" LOC = A16 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;

######################################################################################################################
# VGA #
######################################################################################################################

NET "HSync" LOC = B12 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"VSync" LOC = A12 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;

NET
"Red[2]" LOC = C9 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"Red[1]" LOC = B9 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"Red[0]" LOC = A9 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;

NET
"Green[2]" LOC = C11 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"Green[1]" LOC = A10 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"Green[0]" LOC = C10 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;

NET
"Blue[2]" LOC = A11 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"Blue[1]" LOC = B11 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;


######################################################################################################################
# HEADER P6 #
######################################################################################################################

NET "IO_P6[0]" LOC = U7 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"IO_P6[1]" LOC = V7 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"IO_P6[2]" LOC = T4 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"IO_P6[3]" LOC = V4 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"IO_P6[4]" LOC = U5 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"IO_P6[5]" LOC = V5 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"IO_P6[6]" LOC = R3 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"IO_P6[7]" LOC = T3 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;

######################################################################################################################
# HEADER P7 #
######################################################################################################################

NET "IO_P7[0]" LOC = U8 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"IO_P7[1]" LOC = V8 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"IO_P7[2]" LOC = R8 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"IO_P7[3]" LOC = T8 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"IO_P7[4]" LOC = R5 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"IO_P7[5]" LOC = T5 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"IO_P7[6]" LOC = T9 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"IO_P7[7]" LOC = V9 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;

######################################################################################################################
# HEADER P8 #
######################################################################################################################

NET "IO_P8[0]" LOC = R11 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"IO_P8[1]" LOC = T11 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"IO_P8[2]" LOC = R10 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"IO_P8[3]" LOC = T10 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"IO_P8[4]" LOC = U13 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"IO_P8[5]" LOC = V13 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"IO_P8[6]" LOC = U11 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"IO_P8[7]" LOC = V11 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;

######################################################################################################################
# HEADER P9 #
######################################################################################################################

NET "IO_P9[0]" LOC = H17 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"IO_P9[1]" LOC = H18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"IO_P9[2]" LOC = J16 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"IO_P9[3]" LOC = J18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"IO_P9[4]" LOC = K15 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"IO_P9[5]" LOC = K16 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"IO_P9[6]" LOC = L15 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET
"IO_P9[7]" LOC = L16 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;

The above can be quite complicated to understand at first.  Lets take away all of the lines we don’t need and then explain what they mean:

#********************************************************************************************************************#
# Implementation Constraints file for Mimas V2 #
#********************************************************************************************************************#

######################################################################################################################
# DIP Switches #
######################################################################################################################

NET "DPSwitch[0]" LOC = C17 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP;

NET "DPSwitch[1]" LOC = C18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP;

######################################################################################################################
# LEDs #
######################################################################################################################
NET "LED[0]"              LOC = P15  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;

NET "LED[7]" LOC = T18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;

Anything preceded by a # is a comment in an implementation constraints file and is ignored by the Xilinx Compiler.

The line NET “DPSwitch[0]” LOC = C17 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; means there is a dipswitch connected between pin C17 and 3.3V, The pin uses a fast slew rate and the internal pullup resistor is enabled.  It’s the same thing for DPSwitch[1]

The line NET “LED[0]” LOC = P15 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; means there is an LED connected between pin P15 and 3.3V, the pin uses a fast slew rate.  It is the same for LED[7]

 What we need to do is change the ‘NET’ names to reflect the VHDL code we have already written.  Copy and paste the code below into the Xilinx ICF code editor:

#********************************************************************************************************************#
# Implementation Constraints file for Mimas V2 #
#********************************************************************************************************************#

######################################################################################################################
DIP Switches
######################################################################################################################
 
   NET "DIP1"         LOC = C17  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP;

NET "DIP2" LOC = C18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP;

###################################################################################################################### LEDs #
######################################################################################################################
NET "LED1" LOC = P15 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;

NET "LED2" LOC = T18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;


The Xilinx project screen should now look like this:

Once you are ready its time to save our work and to implement the top level – Click on the arrow on the left side of the screen:

If everything went as planned there should be green arrows present in the bottom left corner.  Now it is time to generate the bit stream file.  This is the binary file that is sent via the programming software to the FPGA to ‘program’ it.  Right click on the ‘Generate Programming File’ option in the bottom left part of the screen and then select ‘Process Properties':

A new window will appear.  ‘Check’ Create Binary Configuration File and then click ‘OK’

Now its time to actually generate the ‘bit stream file’….right click on the Generate Programming File’ option and select ‘Run’…

Once that is complete we can close down Xilinx 14.7 and load up the Mimas V2 programming software.  Navigate to where you downloaded the Mimas V2 files earlier – we are looking for the MimasV2Config.exe application.  For ease of use I made a shortcut and ‘pinned it’ to the start menu:

Next we need to connect the MimasV2 development board to a suitable USB port and install the USB driver.  I’ve done this already, if you haven’t when you plug in the development board you will be prompted by windows to locate the driver file.  It’s in the numatoCDC folder.  Once that’s sorted we need to find out the COM port for the Mimas V2 board.   Click on ‘Devices and printers’ from the start menu.  If the driver and board have been correctly loaded it should be present in the unspecified section:

Double click on the ICON highlighted and a window will appear showing the COM Port number:

Make a note of the COM port number as we will need it to program the development board.  Load up the MimasV2Config software and select the COM port:

Now click on the ‘Open File’ button and navigate to the project folder which contains the bit stream file we just created.  It should have a .BIN extension:

Click the ‘Open’ button and then click the ‘Program’ button – Exciting times!

Once programming has completed (it took a good 30 seconds) all of the LEDS should be OFF except LED1 and LED8.  When you change the state of DIP switches 1 and 2, LED1 and LED8 should go ‘OFF’!

And when we change DIP1 and DIP2….nothing happens!  I found that it was DIP7 and DIP 8 which cause the LEDS to go OFF.

This suggests there is something incorrect with the implementation constraints file and the schematic diagram!  I suspect the connections have been reversed and DIP1 and DIP2 are connected to pins F17 and F18.  I also noticed that the seven segment display is ‘Ghosting’ – it is slightly on when it should be….Lets fix that by modifying the VHDL code and lets modify the implementation constraints file to use the correct switches.  Lets also reverse the logic so that when the switches are ‘Off’ the LEDS are ‘Off’ and when the switches are ‘ON’ the LEDS are ‘ON’.

Here is the new VHDL code which needs pasting into the VHDL source file:

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-- Alex's Mimas V2 VHDL Tutorial
-- (c) 21-12-2014
-- A simple demonstration of a development board

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Mimas_V2_VHDL_Tutorial is
Port (
DIP1 : in STD_LOGIC;
DIP2 : in STD_LOGIC;

LED1 : out STD_LOGIC;
LED2 : out STD_LOGIC;


-- Enable the control pins for the seven segment display
SevenSegmentEnable0 : out STD_LOGIC;
SevenSegmentEnable1 : out STD_LOGIC;
SevenSegmentEnable2 : out STD_LOGIC);

end Mimas_V2_VHDL_Tutorial;

architecture Behavioral of Mimas_V2_VHDL_Tutorial is

begin

LED1 <= NOT DIP1;
LED2 <= NOT DIP2;

-- set seven segment display to OFF

SevenSegmentEnable0 <= '1';
SevenSegmentEnable1 <= '1';
SevenSegmentEnable2 <= '1';

end Behavioral;
Next we need to modify the implementation constraints file with the following code:
#*****************************************************************************************## Implementation Constraints file for Mimas V2 ##*****************************************************************************************# ###########################################################################################
# DIP Switches ############################################################################################ NET “DIP1″ LOC = F18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; NET “DIP2″ LOC = F17 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; ############################################################################################ LEDS #
###########################################################################################
NET “LED1″ LOC = P15 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; NET “LED2″ LOC = T18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; ############################################################################################ Seven Segment Enable ############################################################################################  
NET “SevenSegmentEnable0″ LOC = B2 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; NET “SevenSegmentEnable1″ LOC = A2 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; NET “SevenSegmentEnable2″ LOC = B3 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;

Once that is done we then need to implement the top level again and generate a new bit-stream file 
and reprogram the device. I’m not going to post pictures….Here is a video instead!


Well….that is all for now. I’ll be writing more posts as I get more familiar with the development board
Thanks for reading and take care always – Langster!

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